* (C) 2023 Tibor 'Igor2' Palinkas
* License: CC0 (no rights reserved): https://creativecommons.org/publicdomain/zero/1.0/
*
* source: https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/

.model bridge_adc_ttl adc_bridge
+      (in_low=0.8 in_high=2.0 rise_delay=1.0e-12 fall_delay=1.0e-12)
